1. Field of the Invention
Embodiments of the invention generally relate to an apparatus and method for polishing or planarization of semiconductor substrates.
2. Description of the Related Art
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, trenches and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conductive, semiconductive, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conductive, semiconductive, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electro-chemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. An example of non-planar process is the deposition of copper films with the ECP process in which the copper topography simply follows the already existing non-planar topography of the wafer surface, especially for lines wider than 10 microns. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Planarization is generally performed using Chemical Mechanical Polishing (CMP) and/or Electro-Chemical Mechanical Deposition (ECMP). A planarization method typically requires that the substrate be mounted in a wafer head, with the surface of the substrate to be polished exposed. The substrate supported by the head is then placed against a rotating polishing pad. The head holding the substrate may also rotate, to provide additional motion between the substrate and the polishing pad surface. Further, a polishing slurry (typically including an abrasive and at least one chemically reactive agent therein, which are selected to enhance the polishing of the topmost film layer of the substrate) is supplied to the pad to provide an abrasive chemical solution at the interface between the pad and the substrate.
The combination of polishing pad characteristics, the specific slurry mixture, and other polishing parameters can provide specific polishing characteristics. Thus, for any material being polished, the pad and slurry combination is theoretically capable of providing a specified finish and flatness on the polished surface. It must be understood that additional polishing parameters, including the relative speed between the substrate and the pad and the force pressing the substrate against the pad, affect the polishing rate, finish, and flatness. Therefore, for a given material whose desired finish is known, an optimal pad and slurry combination may be selected. Typically, the actual polishing pad and slurry combination selected for a given material is based on a trade off between the polishing rate, which determines in large part the throughput of wafers through the apparatus, and the need to provide a particular desired finish and flatness on the surface of the substrate.
Because the flatness and surface finish of the polished layer is dictated by other processing conditions in subsequent fabrication steps, throughput insofar as it involves polishing rate must often be sacrificed in this trade off. Nonetheless, high throughput is essential in the commercial market since the cost of the polishing equipment must be amortized over the number of wafers being produced. Of course, high throughput must be balanced against the cost and complexity of the machinery being used. Similarly, floor space and operator time required for the operation and maintenance of the polishing equipment incur costs that must be included in the sale price. For all these reasons, a polishing apparatus is needed which has high throughput, is relatively simple and inexpensive, occupies little-floor space, and requires minimal operator control and maintenance.
Multiple polishing steps have been used for polishing the substrate to thereby allow improved polishing rate and finish with multiple pad or slurry combinations, hence increasing throughput.
One method provides a main polishing surface and a fine polishing surface in a polishing apparatus. A single polishing head, controlled by a single positioning apparatus, moves a single substrate between the different polishing stations on the apparatus. However, at least one polishing surface is idle at any given time.
Another method provides multiple polishing pads, each pad corresponding to a polishing head, and a substrate handling device moving the substrate being processed among the polishing pads and heads. However, multiple loading and unloading of substrates limits the throughput and also increases the possibility of particle contamination.
Another method of increasing throughput uses a wafer head having a plurality of substrate loading stations therein to simultaneously load a plurality of substrates against a single polishing pad to enable simultaneous polishing of the substrates on the single polishing pad. Although this method would appear to provide substantial throughput increases over the single substrate style of wafer head, several factors militate against the use of such carrier arrangements for planarizing substrates, particularly after deposition layers have been formed thereon. First, the wafer head holding the wafer being polished is complex. To attempt to control the force loading each substrate against the pad, one approach floats the portion of the head holding the wafer. A floating wafer holder necessitates a substantial number of moving parts and pressure lines must be included in the rotating and moving geometry. Additionally, the ability to control the forces pressing each individual substrate against the pad is limited by the floating nature of such a wafer head assembly, and therefore is a compromise between individual control and ease of controlling the general polishing attributes of the multiple substrates. Finally, if any one substrate develops a problem, such as if a substrate cracks, a broken piece of the substrate may come loose and destroy all of the other substrates being polished on the same pad.
Polishing throughput is yet further limited by the requirement that wafers be washed at the end of polishing and between stages of polishing especially when non-compatible polishing solutions are used in different polishing stages. Although washing time has been limited in the past by simultaneously washing multiple wafer head, insofar as the washing requires additional machine time over that required for polishing, system throughput is adversely affected.
Therefore, there is a need for a polishing apparatus which enables optimization of polishing throughput.